Basic concept of calculating the GRO-TDC output by differentiating phase. | Download Scientific Diagram
![Figure 10 from A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping | Semantic Scholar Figure 10 from A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/fc336fa24145e8240b65c34f37612e7bdc21e1dc/6-Figure10-1.png)
Figure 10 from A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping | Semantic Scholar
![Figure 3 from A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology | Semantic Scholar Figure 3 from A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/687e990ebc74fa5a90abdd6f090e0151104ce5c7/2-Figure3-1.png)
Figure 3 from A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology | Semantic Scholar
![Sensors | Free Full-Text | A Cyclic Vernier Two-Step TDC for High Input Range Time-of-Flight Sensor Using Startup Time Correction Technique Sensors | Free Full-Text | A Cyclic Vernier Two-Step TDC for High Input Range Time-of-Flight Sensor Using Startup Time Correction Technique](https://www.mdpi.com/sensors/sensors-18-03948/article_deploy/html/images/sensors-18-03948-g005.png)
Sensors | Free Full-Text | A Cyclic Vernier Two-Step TDC for High Input Range Time-of-Flight Sensor Using Startup Time Correction Technique
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Figure 2 from A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps | Semantic Scholar
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Figure 11 from A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping | Semantic Scholar
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